Server-Class Open ISA Cores
High-performance, many-core processor designs built on the open instruction set bring licence-free silicon into data centre and cloud server sockets previously reserved for proprietary architectures.
Developed mainly in: China and United StatesImpacting: North America, Europe, China and Rest of Asia
A RISC-V daily digest reports SpacemiT and the open-source XiangShan project jointly launching V100, described as the first chip fully compliant with the RISC-V server platform specification. The same window saw Tenstorrent close a $1.5bn Series E at a $6.2bn post-money valuation, ZTE's Lizrui Micro reveal the Everest 200 datacentre CPU, and Linux 7.3 add RVA23 support.
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First flagged
30 October 2026 · score 7.0/10
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Tracked from 2 signals, each traced to its source.
- First server-class CPU claiming full RISC-V server platform specification compliance unveiled
Kubuds · 1 Nov 2026
- Capital and acquisitions push RISC-V toward high-performance data centre processors
Meticulousresearch · 30 Oct 2026
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